1. Devices with Master capability can identify themselves
to other specific Master devices and advise their
own specific address and functionality.
2. Only two devices exchange data during one 'conversation'
The trick of open-drain lines & pull-up resistors:
The bus interface in I²C is built around an input
buffer and an open drain transistor. When the bus is in
"idle" state, the bus lines are kept in the logic
"high" state. The external pull-up resistors are
used for this condition to achieve. This pull-up resistor
as seen in the fig-1 is actually a small current source.
If the device wants to put a signal on the bus, the chip
drives its output transistor, thus pulling the bus to "low"
level. Suppose the bus is already occupied by another chip
by sending a "low" state to the bus. Then all
other chips lose their right to access the bus. The chip
does this with a built-in bus mastering technique.
Both the bus lines SDA and SCL are initially bi-directional.
This means that in a particular device, these lines can
be driven by the IC itself or from an external device. In
order to achieve this functionality, these signals use open
collector or open drain outputs.
The weak point of open-collector technique is, in a lengthy
bus the speed of transmission comes down drastically due
to the presence of capacitive load. The shapes of the signals
alter in proportion to RC time constant. Higher the RC constant,
the slower will be the transmission. At some point, the
ICs will not be able to sense logic 1 and 0.
And also it can cause reflections at high speed, which
creates "ghost signals" and corrupt the data,
which is being transmitted.
This problem can be overcome by using an active I²C
terminator. This device consists of a twin charge pump,
which can be considered as a dynamic resistor (instead of
the passive pull-up resistors used). The moment the state
changes, it provides a large current (low dynamic resistance)
to the bus. This action will charge the parasitic capacitor
very quickly. Once the voltage has risen above a certain
level, the high current mode cuts out and the output current
Different states, conditions & events on the bus:
We saw several unique states and conditions on the bus
in our explanation: START, ADDRESS, ACK, DATA and STOP.
Let us now try to understand some more about those states.
The Start state needs to be issued on the bus before any
type of transaction on the bus. The master-chip first pulls
the data line (SDA) low, and next pulls the clock line (SCL)
low. This condition is a signal to all the connected chips
to listen to the bus to expect a transmission.
A single message can contain multiple Start conditions.
The use of this is called "repeated start".
ADDRESS & DATA:
After the "start" bit, a byte (7+1) is transmitted
to slaves by the master. This byte is the address, which
can identify the particular slave on the bus. Bit 0 of this
byte determines the slave access mode ('1' = read / '0'
= write). Remember, bytes are always transmitted MSB first.
The R/W bit '0' indicates the master is willing to send
data to the slaves. Then the intended slave will respond
back with ACK signal, indicating that its ready to receive.
And the communication continues.
In the same way, a byte can be received from the slave
if the R/W bit in the address was set to '1', i.e. 'read'.
But now the master is not allowed to touch the SDA line.
Master sends the 8 clock pulses needed to clock in a byte
on the SCL line, and releases the SDA line. Instead, the
slave will now take control of this SDA line for data transfer.
All the master has to do now is generate a rising edge on
the SCL line, read the level on SDA and generate a falling
edge on the SCL line. The slave will not change the data
during the time that SCL is high. This sequence has to be
performed 8 times to complete the data byte.
Some of the addresses are reserved for "extended addressing
mode", which use 10-bit addressing. If a standard slave
node, which is not able to resolve this extended addressing
receives this address, it won't do anything.
As we know the ACK signal is send back to the master whenever
the address or data byte has been transmitted onto the bus
and received by the intended slave node.
The slave after sending ACK signal will drive the SDA line
to low status immediately after receiving the 8th data bit
transmitted by the master or after evaluating received address
byte. So to signal the completion of transmission, SCL pulled
to low by master, whereas SDA is pulled to low by slave.
To repeat the transmission, master drops a clock pulse
on the SCL line and slave will release the SDA line after
receiving the clock. With this, bus is now ready again for
master to send data or to initiate a stop condition.
In the same way, the master must acknowledge the slave
device upon successful reception of a byte from a slave.
SDA and the SCL line are in full control of the master.
The slave will release the SDA line after sending last bit
to the master and make the SDA line high. The Master will
now bring the SDA line low state and put a clock pulse on
the SCL line. After completion of this clock pulse, the
master will again release the SDA line to allow the slave
to regain control of the SDA line.
The master can stop receiving data from the slave at any
time, just by sending a stop condition.
NACK means "Not Acknowledge". Confused? Don't
confuse it with "No Acknowledge". Because, "Not
Acknowledge" occurs only after a master has read a
byte from a slave. And "No Acknowledge" occurs
after a master has written a byte to a slave. Again confused?
Lets analyze this in detail.
This happens when the slave regains control of the SDA line
after the ACK cycle issued by the master.
Let's assume the next bit ready to be sent to the master
is a 0. The slave would pull the SDA line low immediately
after the master takes the SCL line low. The master now
attempts to generate a Stop condition on the bus. It releases
the SCL line first and then tries to release the SDA line,
which is held low by the slave. So in short, No Stop condition
has been generated on the bus. This condition is called
If, after transmission of the 8th bit from the master to
the slave the slave does not pull the SDA line low, then
this is considered a No ACK condition.
This condition may be created due to the following reasons:
1. The slave is not there (in case of an address)
2. The slave missed a pulse and got out of sync with the
SCL line of the master.
3. The bus is "stuck". One of the lines could
be held low permanently.
In any case the master should abort by attempting to send
a stop condition on the bus.
The stop state is sent to the bus only after the message
transfer has been completed. The master-MCU first releases
the SCL and then the SDA line. This condition is a true
indication to all the chips and devices on the bus that
the bus is idle or the bus is free and available again for
A Stop condition denotes the END of a transmission, even
if it is issued in the middle of a transaction or in the
middle of a byte. In this case, the chip disregards the
information sent and goes to IDLE-state, waiting for a new
Modes of operation:
The I²C bus can operate in three modes, or in other
words the data on the I2C bus can be transferred in three
1. Standard mode
2. Fast mode
3. High-Speed (Hs) mode
1. This is the original Standard mode released in early
2. It has maximum data rates of 100kbps
3. It uses 7-bit addressing, which provides 112 slave addresses.
Enhanced or Fast mode:
The fast mode added some more features to the slave devices.
1. The maximum data rate was increased to 400kbps.
2. To suppress noise spikes, Fast-mode devices were given
3. The SCL and SDA lines of an I²C-bus slave device
were made to exhibit high impedance when power was removed.
This mode was created mainly to increase the data rate
up to 36 times faster than standard mode. It provides 1.7
Mbps (with C>b = 400pF), and 3.4Mbps (with C>b = 100pF).
The major difference between High Speed (HS) mode in comparison
to standard mode is, HS mode systems must include active
pull up resistors on the SCL line. The other difference
is, the master operating in HS -mode sends a compatibility
request signal in code form to slave, if not-Acknowledge
(a bit name with in the I2C frame) remains high after receiving
the compatibility code, than the master assumes the slave
is capable of HS-mode.
The risk of data corruption:
The operation of the bus with one master node seems to
be very easy. But what happens if there are two masters
connected to the bus and if both of them start communicating
at the same time. Let us try to analyze this situation in
When the first MCU issues a start condition and sends an
address, all slaves will listen (including the second MCU
which at that time is considered a slave as well). If the
address does not match the address of the second MCU, it
will hold back any activity until the bus becomes idle again
after a stop condition.
As long as the two MCU's monitor what is going on, on the
bus (start and stop) and as long as they are aware that
a transaction is going on because the last issued command
was not a STOP, there is no problem.
But, what will happen if one of the MCU's missed the START
condition and still thinks the bus is idle, or it just came
out of reset and wants to communicate.
The physical bus setup of the I²C helps to solve this
problem. Since the bus structure is a wired AND (if one
device pulls a line low it stays low), its possible to find
whether the bus is idle or occupied.
Different versions of the I2C bus
Some of the specifications of the different versions of
the I2C bus are explained below.
Version 1.0 - 1992
1. Programming of a slave address by software has been
2. The "low-speed mode" has been omitted.
3. The Fast-mode is added. Fast-mode devices are downward
4. 10-bit addressing is added. This allows 1024 additional
5. Slope control and input filtering for Fast-mode devices
is specified to improve the EMC behaviour.
Version 2.0 - 1998
1. The High-speed mode (Hs-mode) is added.
2. The low output level and hysteresis of devices with a
supply voltage of 2 V and below has been adapted to meet
the required noise margins and to remain compatible with
higher supply voltage devices.
3. The 0.6 V at 6 mA requirement for the output stages of
Fast-mode devices has been omitted.
4. The fixed input levels for new devices are replaced by
bus voltage-related levels.
5. Application information for bi-directional level shifter
Version 2.1 - 2000
1. After a repeated START condition in Hs-mode, it is possible
to stretch the clock signal SCLH (see Section 13.2 and Figs
22, 25 and 32).
2. Some timing parameters in Hs-mode have been relaxed
Benefits and Drawbacks:
Since only two wires are required, I2C is well suited for
boards with many devices connected on the bus. This helps
reduce the cost and complexity of the circuit as additional
devices are added to the system.
Due to the presence of only two wires, there is additional
complexity in handling the overhead of addressing and acknowledgments.
This can be inefficient in simple configurations and a direct-link
interface such as SPI might be preferred.
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