the fabrication of MOSFET, the minimum channel length has been shrinking continuously.
The motivation behind this decrease has been an increasing interest in high-speed
devices and in very large-scale integrated circuits. The sustained scaling of
conventional bulk device requires innovations to circumvent the barriers of fundamental
physics constraining the conventional MOSFET device structure. The limits most
often cited are control of the density and location of dopants providing high
I on /I off ratio and finite sub threshold slope and quantum-mechanical tunneling
of carriers through thin gate from drain to source and from drain to body. The
channel depletion width must scale with the channel length to contain the off-state
leakage I off. This leads to high doping concentration, which degrade the carrier
mobility and causes junction edge leakage due to tunneling. Furthermore, the dopant
profile control, in terms of depth and steepness, becomes much more difficult.
The gate oxide thickness tox must also scale with the channel length to maintain
gate control, proper threshold voltage VT and performance. The thinning of the
gate dielectric results in gate tunneling leakage, degrading the circuit performance,
power and noise margin. Alternative device structures based on silicon-on-insulator
(SOI) technology have emerged as an effective means of extending MOS scaling beyond
bulk limits for mainstream high-performance or low-power applications .Partially
depleted (PD) SOIwas the first SOI technology introduced for high-performance
microprocessor applications. The ultra-thin-body fully depleted (FD) SOI and the
non-planar FinFET device structures promise to be the potential "future"
technology/device choices. In these device structures, the short-channel effect
is controlled by geometry, and the thin Si film limits the off-state leakage.