The Data Bus and the "B"-register are added together, with the result stored in the ALU Output Cache Register.
The ADD instruction treats the Data Bus as the "left side" of the addition, and the "B" register as the "right side". The reasoning for this is the "left side" has Decrement and Shift Left functionality that is missing from the "right side". When performing sequential decrements or shifts, this will save a transfer operation to copy the Output Cache Register to the "A" register.
When the ADD instruction sources memory for the "B" side of the equation, the source device must be main memory (binary id: 0011, hex id: 3), or the supplied 16-bit number will be ignored.
Hex Mnemonic Action
0910 ; ADD PC, B PC + B -> OCR
09A0 ; ADD A, B A + B -> OCR
09F0 ; ADD OCR, B OCR + B -> OCR
0930 ; ADD #4E1C, B 4E1C + B -> OCR
Updates when Executed:
- ALU Output Cache Register
- Carry Flag
- Zero Flag
- Negative Flag