Last month, the first half of this article introduced the large-signal approach to oscillator design. This concluding section will offer some VHF/ UHF design examples, including the 144-MHz oscillator first presented last month in Part 1.
The component values for the 144-MHz oscillator (C1, C2, C3, C4, and L) can be calculated in the following way. First, the values of capacitors C1 and C2 can be found from the following approach. The value of capacitor C1 is selected for proper loading according to Eq. 32 (see box 1 for equation).
If using a ratio of C1/C2 = 4, then the value of capacitor C2 is approximately 11 pF.
The values for capacitors C3 and C4 can be found by again choosing for optimum phase noise and output power, in which case:
and the capacitive transformer tapping ratio m (C3/C4) should be greater than 10; therefore, the impedance transformation is greater than 100. Thus, for a value of C3 of 22 pF, the value of C4 is 220 pF. Again one needs to use as many as 10 parallel capacitors or a very low-parasitic one that is capacitive to more then 1 GHz.
The L/C ratio for the 144-MHz oscillator can be calculated in the following way. The energy stored across the resonator circuit for a given conduction angle and drive level is dependent on the characteristic impedance, and can be found from Eq. 36 (see box 1 for equation).
For optimum phase noise and output power, Z should be greater than 3. For example, the L/C ratio for a good approach is
The same test circuit for the small-signal analysis can now be used with the new large-signal component values applied. Reference 9 shows the phase-noise calculations for a Colpitts oscillator. The calculations can also be used to find the phase noise for the 144-MHz oscillator circuit. Using the Nexxim HB simulator from Ansoft Designer, the simulated phase noise agrees closely with measured data.
According to ref. 9, the individual phase noise contribution can be described by using Eq. 38 (see box 1 for equation), as well as Eqs. 39-42 (see box 2 for equations). The total effect of all the four noise sources can be expressed as the function shown in Eq. 43 (see box 3 for equation).
Kf = the flicker noise constant,
AF = the flicker noise exponent, and
It should be noted that the effect of the loading of the Q of the resonator is calculated by the noise transfer function multiplied with the sum of the four noise sources.
The next step for the 144-MHz oscillator is to compute the phase-noise contribution from the different noise sources for the parallel tuned Colpitts oscillator circuit at a frequency offset of 10 kHz from the oscillator carrier frequency (f0) of 144 MHz. This is performed by considering the circuit parameters. For example, the base resistance (rb of the transistor is 6.14 ohms while the parallel loss resistance of the resonator (RP is 7056 ohms. The Q of the resonator (the Q of the inductor at 144 MHz) is 200, the inductance of the resonator is 39 nH, and the capacitance of the resonator is 22 pF. The transistor collector current (Ic) is 10 mA while the base current of the transistor (Ib) is 85 A. The device flicker noise component (AF) is 2 while the flicker noise constant (Kf) is 1 10-7. The feedback factor (n) is 5. The phase noise at an offset frequency of 10 kHz for the four noise sources can be found by applying Eqs. 45, 46, 47, and 48 (see the box 4 for equations).
The sum of the four noise sources can be expressed as expressed in the relationship shown as Eq. 49 (shown in box 5).
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It should be noted that the noise contribution from the resonator is the limiting factor. For low-Q cases, this can be identified as the flicker corner frequency. When evaluating closer-in phase noise, at an offset of 100 Hz, we have the relationships shown in Eqs. 50 and 51 below:
as well as Eqs. 52 and 53 (shown in the box 4).
The sum of the four noise sources can be expressed by Eq. 54 (shown at the bottom of the box 4).
It appears the collector current, base resistance noise flicker noise from the transistor, and the noise from the resonator are the limiting factors for the overall oscillator phase noise.
Figure 8 and figure 9 show the schematic and layout of the 144 MHz oscillator using time-domain parameters for Ic = 10 mA. The oscillator circuit of Fig. 8 uses a lumped inductor of 39 nH and an unloaded Q of 200 at the operating frequency. The layout is quite critical even at this frequency. The layout in Fig. 8 shows component assembly where lead inductances have been kept small. A standard off-the-shelf inductor was used in the oscillator.
Figure 10, figure 11, and figure 12 show the CAE simulated phase noise plot, the measured phase noise plot, and the simulated output power for the 144-MHz oscillator using the large-signal approach. The simulated and validated output power is +11.55 dBm (a 6-dB improvement over the linear case) and, at 10 kHz offset from the carrier frequency, the phase noise is 135 dBc/Hz, a 13-dB improvement from the value of 122 dBc/Hz for the small-signal, linear approach.
By applying the phase-noise calculation approach used earlier, the phase noise levels for the large-signal 144-MHz oscillator are found to be -134 dBc/Hz offset 10 kHz from the carrier frequency and -94 dBc/Hz offset 100 Hz from the carrier frequency. The calculated, simulated, and measured results all agreed within 1 dB. For designers not having access to expensive CAE tools with the proper oscillator noise-calculation capabilities, this approach with its capabilities of calculating phase noise can be quite useful and cost-effective.
If the same transistor is now run at 30 mA, the phase noise offset 10 kHz from the carrier will improve further to 144 dBc/Hz with the oscillator's output power increased to +20 dBm at 144 MHz. This demonstrates that choosing a high-output transistor can aid in achieving a low-phase-noise oscillator design. Still, it is important to consider the device's DC dissipation, since a CAE software tool will not flag a misuse of the device in this way.
A second, higher-frequency, 433- MHz oscillator example may help to further demonstrate the usefulness of the large-signal oscillator design approach. The same transistor (Infineon model BFR193) can be used as in the earlier example, with device parameters of Vce = 8.8 V, Ic =10 mA, IB = pA, and Vbe = 0.67 V. The same set of design equations and conditions at this frequency yield C1 = 3.3 pF, C2 = 13 pF, C3 = 7.5 pF, C4 = 7.5 pF, C3B = 75 pF, LE = 13 nH, RE = 320 ohms, RB1 = 29000 ohms, RB2 = 20000 ohms, CB = 220 pF, Cc = 1000 pF, and VDC = 12 V.
These values result in an output power of +11.9 dBm and phase noise of 100 dBc/Hz offset 10 kHz from the carrier. The 144-MHz oscillator yielded about 35 dB drop in phase noise (-135 dBc/Hz offset 10 kHz from the carrier), although such a drop-off in phase seems unusual. The phase noise and the carrier frequency are related in a quadratic fashion, so that a three times increase in carrier frequency will result in a 9-dB degradation in phase noise (as shown in Fig. 8 for a comparison of a 432-MHz oscillator with a 144-MHz oscillator). Therefore, the phase noise for a 432-MHz oscillator circuit should be -126 dBc/Hz rather than the CAE-simulated -100 dBc/Hz offset 10 kHz from the carrier for the 433-MHz oscillator. The answer lies in the fact that that even in a grounded-base condition, the large signal Re loads the parallel tuned circuit significantly, resulting in a lower dynamic operating Q. This is a limitation that must be overcome.
Because phase noise and Q are related in a quadratic function, a doubling of Q results in a 12-dB improvement in phase noise. Since 26 dB phase noise was lost in the switch to the higher-frequency oscillator design, the dynamic loaded operating Q must be improved by about 20 times the initial value. Since this cannot be done, it may be possible to find effects other than the deterioration in Q that effect the phase noise. One answer is that "the collector emitter capacitance dynamically detunes the circuit periodically." A solution for this problem is to tap the inductor, therefore, decreasing the influence of the transistor.
An inspection of the parameters for the oscillator transistor at 432 MHz and 30 mA will reveal that loading of the tank circuit decreases the operating Q significantly. The way around this is to apply a center-tapped inductor. As the coupling at these frequencies from winding to winding is not extremely high, two separate identical inductors can be used for this purpose. Figure 13 shows the schematic diagram of the 432-MHz grounded base oscillator using the tapped inductor, a modification of the oscillator circuit used previously. In the case of a VCO, it would be advantageous to use a different outputcoupling scheme since the loading would vary with frequency. This can easily be achieved by adding inductive coupling, such as a printed resonator, to the oscillator circuit.
Figure 14 shows the layout of the 433-MHz oscillator circuit using a buried printed coupled-line resonator network (with a stripline resonator in the middle layer of the circuit board).
The actual resonator would not be visible if performing a visual inspection of the oscillator.
Figure 15 offers a plot of simulated phase noise. It shows the expected noise degradation of 9 dB, since the frequency is approximately three times higher than the earlier example (144 MHz). The resulting simulated output power at 432 MHz is +16 dBm, compared to +18 dBm for the 144-MHz oscillator. This is due to internal package parasitics, which could not be compensated for externally. Second harmonics are suppressed by 38 dB due to the higher operating Q.
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The results obtained so far were based on mathematical calculations, some difficult to obtain. However, by inspecting the resulting circuits, there are certain relationship between the values of the capacitance of the tuned circuit and the two feedback capacitors, the collector emitter capacitor and the emitter to ground capacitor. The following shows the set of recommended steps for easy design of such oscillator. Figure 16 shows the typical grounded base oscillator for demonstrating the simple design rules where CE and CF are the feedback capacitors that generate the negative resistance to compensates the loss resistance of the resonator network comprised of inductor LE and capacitance C*L.
By setting the L/C ratio to a fixed value of 1200 (this is done for optimum energy storage, group delay and energy transfer for a given cycle in the resonator network), the sequence of equations represented by Eq. 55 (see box 6) and Eqs. 57, 58, 59, and 60 below should be used:
The accuracy of this simple approach can be evaluated by applying it to the 144-MHz grounded-base oscillator from Fig. 10 (radio amateurs reading this article will certainly appreciate this oscillator example), using the relationships represented in Eqs. 61-67 shown below:
These results are comparable with the results above and the calculation is frequency scalable with minor corrections possibly, if necessary. Competing other alternative short formulae published in the literature may not deliver the same high performance.
Many modern applications require high-performance, low-cost oscillators and design time is critical for realizing these components. The approach shown here meets these requirements and gives detailed guidelines for better-performing oscillators. Several examples have been presented for the approach, but it can be applied to a wide range of different frequencies and oscillators. In addition, the design approach can be readily translated to integrated-circuit designs to achieve extremely small, low-cost oscillators. The equations used in the calculations are fairly simple and provide accurate predictions of phase noise and output power for frequencies to about 200 MHz. At frequencies above about 500 MHz, nonlinear CAE tools should be applied.
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