University of Idaho
One of the main reasons for the difficulty of hardware verification is that hardware platforms are typically nondeterministic at clock-cycle granularity. Uninitialized state elements, I/O, and timing variations on high-speed buses all introduce non-determinism that causes different behavior on different runs starting from the same initial state. To improve the authors' ability to debug hardware, they would like to completely eliminate non-determinism. This paper introduces the Cycle-Accurate Deterministic REplay (CADRE) architecture, which cost-effectively makes a board-level computer cycle-accurate deterministic.