You have 2 Flip-Flops. Each of them can have 2 states.
So your entire Verilog code has 2^2 = 4 states:
- QA=0, QB=0
- QA=0, QB=1
- QA=1, QB=0
- QA=1, QB=1
By using the "CLR" input you get into the state QA=0, QB=0 from anywhere.
The output of your code is "QA". So two of these states have an output of 0 and two of them have an output of 1.
For each of the 4 states you'll have to think what happens when a clock pulse comes and the input is 0 and what happens when the input is 1.
From each of the 4 states you will have (up to) two transitions to another state. Depending on the notation you use you either draw an arrow from a state to the same state or you don't draw the corresponding arrow at all if the state does not change.
As far as I didn't do a mistake the state after the reset (QA=0, QB=0) cannot be left any more.
Xilinx Verilog compilers and synthesis tools can recognize a properly written FSM and create a diagram in graphics format. You can download a WebPack ICE version for free. Synplify tools also used to extract FSM from Verilog code. I am sure there are other tools.
However, the tools expect certain code style and discipline to do so automatically. A well-written FSM usually contains three "always" blocks, see this classic publication. Your code has no resemblance to anything, that's probably why you have a difficulty to identify states and transitions.