Some of the major consumers of NVM technologies are micro-controller units (MCUs), which are small single-chip computers containing one or multiple processor cores, different kinds NVM memories, and programmable input and output peripherals. If we confine our discussion to conventional semiconductor-based NVMs in use today in typical MCUs, the simplest NVM is read-only memory (ROM), which uses a pre-programmed MOSFET and contact/via to store a zero or one data level. The programming is done during manufacture of the product, and thus cannot be altered. Electrically eraseable programmable ROM (EEPROM) allows the data to be erased and re-written in the application.
Flash memory is simply a special version of EEPROM that requires the erase operation to be performed on large portions of the memory at one time, in order to greatly reduce the chip area required per bit. Flash memory thus can be written one byte or word at a time, but erase operations will affect a large portion, called a sector or block. The sector or block size ranges typically from 1 KB to 256 KB. Contents are changed by erasing a sector, then writing fresh data to one or more locations—hence, the name “flash,” since the contents of a whole memory array or memory block are erased in a single step.
To avoid the cost of external memories, MCUs come with on-chip program memory. Originally, these were EPROMs that had a window on the top of the device, where the program memory could be erased by ultraviolet light, and then reprogrammed (this was also called a burn cycle). Since the 1990s, EPROM has been replaced by EEPROM and flash, which are easier to use and cheaper to package. Today MCUs include SRAM for data storage, as well as NVM/flash for program storage, and even EEPROM or EEPROM emulation space, using flash technology (see figure 2).
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Figure 2: MCUs use multiple types of memory. This entry-level MCU from the Kinetis line, for example, includes 32 KB to 128 KB flash, up to 16 KB of SRAM, and the equivalent of up to 2 KB of user-segmentable byte write/erase EEPROM for data tables/system data.
Within the category of flash memory, there are two major architectures: NOR and NAND. NOR flash architecture connects all of the bits along a column of the memory array in parallel, similar to the pull-down portion of a NOR logic gate. NOR flash provides the best read and write performance, but each bit typically requires a dedicated contact to the bitline, thus limiting how small the bit can be made.
NAND flash architecture involves wiring a string of bits within the memory array in series, similar to the pull-down portion of a NAND logic gate. This eliminates the need for dedicated contacts in each bit and allows NAND to achieve the lowest area (and thus cost) per bit, with some compromises in read and write performance, operating range, and robustness.
Another way to divide the usage of flash memory is to distinguish between discrete flash (external to the chip containing the processor) and embedded flash (in which the flash is ‘embedded’ on the same piece of silicon as the processor). Discrete flash is used where a large amount of flash memory (say 32 MB or more) is needed at a low overall system cost, while embedded flash is used when a more moderate amount of flash memory (8 KB to 8 MB, perhaps 16 MB in future systems) is needed, and where the unique advantages gained by embedding the flash are desired. These advantages include lower latency and higher bandwidth for executing code out of the flash memory, reduced power consumption, reduced electromagnetic emissions, enhanced security of code and data, and optimization of the flash design to meet a specific product’s application.
Because NOR flash matches the requirements of embedded flash applications (moderate byte count but enhanced performance, operating range and robustness), NOR architectures are almost always used in embedded flash applications.