dynamic RAM ==>
dynamic random access memory
<storage> (DRAM) A type of semiconductor memory in which the information
is stored in capacitors on a MOS integrated circuit. Typically each bit is
stored as an amount of electrical charge in a storage cell consisting of a
capacitor and a transistor. Due to leakage the capacitor discharges gradually
and the memory cell loses the information. Therefore, to preserve the
information, the memory has to be refreshed periodically. Despite this
inconvenience, the DRAM is a very popular memory technology because of its high
density and consequent low price.
The first commercially available DRAM chip was the Intel 1103, introduced in
The early DRAM chips up to a 16k x 1 (16384 locations of one bit each) model
needed 3 supply voltages (+5V, -5V and +12V). Beginning with the 64 kilobit
chips, charge pumps were included on-chip to create the necessary supply
voltages out of a single +5V supply. This was necessary to fit the device into a
16-pin DIL package, which was the preferred package at the time, and also made
them easier to use.
To reduce the pin count, thereby helping miniaturisation, DRAMs generally had a
single data line which meant that a computer with an N bit wide data bus needed
a "bank" of (at least) N DRAM chips. In a bank, the address and control signals
of all chips were common and the data line of each chip was connected to one of
the data bus lines.
Beginning with the 256 kilobit DRAM, a tendency toward surface mount packaging
arose and DRAMs with more than one data line appeared (e.g. 64k x 4), reducing
the number of chips per bank. This trend has continued and DRAM chips with up to
36 data lines are available today. Furthermore, together with surface mount
packages, memory manufacturers began to offer memory modules, where a bank of
memory chips was preassembled on a little printed circuit board (SIP = Single
Inline Pin Module, SIMM = Single Inline Memory Module, DIMM = Dual Inline Memory
Module). Today, this is the preferred way to buy memory for workstations and
DRAM bit cells are arranged on a chip in a grid of rows and columns where the
number of rows and columns are usually a power of two. Often, but not always,
the number of rows and columns is the same. A one megabit device would then have
1024 x 1024 memory cells. A single memory cell can be selected by a 10-bit row
address and a 10-bit column address.
To access a memory cell, one entire row of cells is selected and its contents
are transferred into an on-chip buffer. This discharges the storage capacitors
in the bit cells. The desired bits are then read or written in the buffer. The
(possibly altered) information is finally written back into the selected row,
thereby refreshing all bits (recharging the capacitors) in the row.
To prevent data loss, all bit cells in the memory need to be refreshed
periodically. This can be done by reading all rows in regular intervals. Most
DRAMs since 1970 have been specified such that one of the rows needs to be
refreshed at least every 15.625 microseconds. For a device with 1024 rows, a
complete refresh of all rows would then take up to 16 ms; in other words, each
cell is guaranteed to hold the data for 16 ms without refresh. Devices with more
rows have accordingly longer retention times.
Many varieties of DRAM exist today. They differ in the way they are interfaced
to the system - the structure of the memory cell itself is essentially the same.
"Traditional" DRAMs have multiplexed address lines and separate data inputs and
outputs. There are three control signals: RAS\ (row address strobe), CAS\
(column address strobe), and WE\ (write enable) (the backslash indicates an
active low signal). Memory access procedes as follows: 1. The control signals
initially all being inactive (high), a memory cycle is started with the row
address applied to the address inputs and a falling edge of RAS\ . This latches
the row address and "opens" the row, transferring the data in the row to the
buffer. The row address can then be removed from the address inputs since it is
latched on-chip. 2. With RAS\ still active, the column address is applied to the
address pins and CAS\ is made active as well. This selects the desired bit or
bits in the row which subsequently appear at the data output(s). By additionally
activating WE\ the data applied to the data inputs can be written into the
selected location in the buffer. 3. Deactivating CAS\ disables the data input
and output again. 4. Deactivating RAS\ causes the data in the buffer to be
written back into the memory array.
Certain timing rules must be obeyed to guarantee reliable operation. 1. RAS\
must remain inactivate for a while before the next memory cycle is started to
provide sufficient time for the storage capacitors to charge (Precharge Time).
2. It takes some time from the falling edge of the RAS\ or CAS\ signals until
the data appears at the data output. This is specified as the Row Access Time
and the Column Access Time. Current DRAM's have Row Access Times of 50-100 ns
and Column Access Times of 15-40 ns. Speed grades usually refer to the former,
more important figure.
Note that the Memory Cycle Time, which is the minimum time from the beginning of
one access to the beginning of the next, is longer than the Row Access Time
(because of the Precharge Time).
Multiplexing the address pins saves pins on the chip, but usually requires
additional logic in the system to properly generate the address and control
signals, not to mention further logic for refresh. Therefore, DRAM chips are
usually preferred when (because of the required memory size) the additional cost
for the control logic is outweighed by the lower price.
Based on these principles, chip designers have developed many varieties to
improve performance or ease system integration of DRAMs:
PSRAMs (Pseudo Static Random Access Memory) are essentially DRAMs with a
built-in address multiplexor and refresh controller. This saves some system
logic and makes the device look like a normal SRAM. This has been popular as a
lower cost alternative for SRAM in embedded systems. It is not a complete SRAM
substitute because it is sometimes busy when doing self-refresh, which can be
Nibble Mode DRAM can supply four successive bits on one data line by clocking
the CAS\ line.
Page Mode DRAM is a standard DRAM where any number of accesses to the currently
open row can be made while the RAS signal is kept active.
Static Column DRAM is similar to Page Mode DRAM, but to access different bits in
the open row, only the column address needs to be changed while the CAS\ signal
stays active. The row buffer essentially behaves like SRAM.
Extended Data Out DRAM (EDO DRAM) can continue to output data from one address
while setting up a new address, for use in pipelined systems.
DRAM used for Video RAM (VRAM) has an additional long shift register that can be
loaded from the row buffer. The shift register can be regarded as a second
interface to the memory that can be operated in parallel to the normal
interface. This is especially useful in frame buffers for CRT displays. These
frame buffers generate a serial data stream that is sent to the CRT to modulate
the electron beam. By using the shift register in the VRAM to generate this
stream, the memory is available to the computer through the normal interface
most of the time for updating the display data, thereby speeding up display data
SDRAM (Synchronous DRAM) adds a separate clock signal to the control signals. It
allows more complex state machines on the chip and high speed "burst" accesses
that clock a series of successive bits out (similar to the nibble mode).
CDRAM (Cached DRAM) adds a separate static RAM array used for caching. It
essentially combines main memory and cache memory in a single chip. The cache
memory controller needs to be added externally.
RDRAM (Rambus DRAM) changes the system interface of DRAM completely. A byte-wide
bus is used for address, data and command transfers. The bus operates at very
high speed: 500 million transfers per second. The chip operates synchronously
with a 250MHz clock. Data is transferred at both rising and falling edges of the
clock. A system with signals at such frequencies must be very carefully
designed, and the signals on the Rambus Channel use nonstandard signal levels,
making it incompatible with standard system logic. These disadvantages are
compensated by a very fast data transfer, especially for burst accesses to a
block of successive locations.
A number of different refresh modes can be included in some of the above device
RAS\ only refresh: a row is refreshed by an ordinary read access without
asserting CAS\. The data output remains disabled.
CAS\ before RAS\ refresh: the device has a built-in counter for the refresh row
address. By activating CAS\ before activating RAS\, this counter is selected to
supply the row address instead of the address inputs.
Self-Refresh: The device is able to generate refresh cycles internally. No
external control signal transitions other than those for bringing the device
into self-refresh mode are needed to maintain data integrity.
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