> Right now I am looking at a registered SDRAM DIMM that says the
> load will be 22 pf for the Address lines and 16.5pf for the data
> lines. If each driver will have 4 loads I can expect 88pf load
> on the address and 66pf load on the data. Therefore my address surly
> needs an 18ma driver and my data a 12ma driver.
> But when I simulate this using QUAD models I get from an extracted
> board for the DIMM module & the memory card I get different feedback.
> The data lines have such a heavy load they need a stronger driver and
> the address lines are lightly loaded and ring like hell with 1 DIMM so
> they need a weaker driver.
> This is what prompted the question in the 1st place.
Driving SDRAM arrays at high speed is *NOT* a cookbook exercise.
I spend almost a third of my time cranking custom driver solutions
for ICs so that they can manage large SDRAM arrays at 100+MHz.
Keep in mind that the impedance that the capacitive loads see is
not so much the driver impedance but the line impedance; no matter
HOW strong the driver is it can only deliver so much transient
current along a 65-ohm trace.
Our best results involve using shunt termination to Vdd/2 on the
SDRAM end of all of the single-cycle lines such as CS, CKE, DQM, etc.
It burns more power but effectively doubles the transient current
by adding turnoff current to turnon current, while halving the
effective impedance seen by the load capacitance.
> At 10:24 AM 3/5/98 -0700, D. C. Sessions wrote:
> >Mark Nass wrote:
> >> Can someone explain to me what driver strength means?
> >That's a good question with no good answer.
> >> When
> >> a driver is spec'd by an ASIC vendor as a 12ma, 6ma, etc what does
> >> that mean
> >Pretty much whatever the vendor wants it to. In some cases the
> >number is more-or-less worst case, sometimes typical, sometimes
> >at useful voltages, sometimes not. At VLSI in our 350nm library
> >the Iol is measured at near-worst-case and 350mv, while the
> >Ioh is measured at 2450mv. Notice that the pullups are weaker
> >than then pulldowns. In our 200nm libraries the numbers are at
> >350mv from the rail for both pullup and pulldown.
> >> as far as its expected VI curve
> >Anybody's guess. Process variables, predriver supplies,
> >possibly architecture, all influence the shape of the V/I
> >curve. About all you can count on is the slope near the rail.
> >> and how many loads
> >> I can expect it to drive?
> >Welcome to the world of signal integrity. You aren't driving
> >the loads, you're driving the wires. If you're willing to wait
> >long enough there's almost no limit on the number of loads even
> >a weak driver can manage.
-- D. C. Sessions email@example.com