Now that 16 nm and 14 nm technologies are coming online, and many semiconductor companies are starting new chip design projects at those nodes, one question that keeps popping up is whether multi-patterning corners are really necessary.
Now that 16-nm and 14-nm technologies are coming online, and many semicondutor companies are starting new chip design projects at those nodes, one question that keeps popping up is whether multi-patterning corners are really necessary.
The post-layout simulation is frequently a big bottleneck for the verification process, and the more corners that are required, the bigger that bottleneck becomes (figure 1).
Figure 1. How many corners are really necessary for chips with multi-patterning? (Source: Mentor Graphics)
Impact of multi-patterning on extraction
Multi-patterning is the technique required for printing geometries that are smaller than the wavelength of light used in manufacturing can accurately resolve. This is typically limited by both the lenses used and the light sources.
To overcome this limitation, polygons on each layer (e.g., metal 1 layer) are split between two or more different masks, as denoted by color assignments (coloring). Printing polygons using multiple masks makes it possible to print smaller geometries than can be printed with just one mask.
However, one of the drawbacks of using multi-patterning is that it is difficult to precisely align the masks.
Any misalignment has an impact on parasitic capacitance, since some wires will be closer together than they should be, causing higher coupling capacitance, whereas other wires will be farther apart, thereby decreasing coupling capacitance.
For example, a 6 nm misalignment causes a 15% error in coupling capacitance and a 5% error on total capacitance, whereas a 2 nm displacement creates approximately a 5% error for coupling capacitance and 2% error for total capacitance . Foundries try to control this mask misalignment as much as possible, but there will always be some misalignment.
Therefore, it is important to characterize the misalignment by doing simulations with the multi-patterning corners, and making sure that the circuit is robust enough to handle the resulting variation.
Colored vs. non-colored parasitic extraction
The parasitic extraction flow to capture multi-patterning effects differs depending on whether or not the layout has already been decomposed into different masks. When deciding on a multi-patterning flow, one major consideration is whether the designer will decompose the layout into the different masks, or whether that step will happen at the foundry.
Different foundries allow different levels of control by their customers for decomposing a layout into multiple masks. Some foundries only require that designs pass multi-patterning space and cycle rule checks, then do the actual decomposition themselves. Other foundries allow customers to tag certain geometries to assign them to a specific mask (a process called anchoring), or even allow customers to fully decompose their designs before tapeout.