Design Rules Check
Extracting the Layout
Layout Versus Schematic Check
The Virtuoso Layout Editing Tool has similar side icons as the Virtuoso Schematic Editing Tool does. Some of the ones that will be used frequently in this tutorial are the rectangle icon (or typing 'r') and the ruler icon (or typing 'k'). The other icons are pretty straight forward to understand and will be referred to if they are needed.
We would like to layout an inverter similar to one we built with existing nmos and pmos parts with the schematic tool. The pmos component we used had W/L parameters of 6um/.6um and the nmos had 3um/.6um. First, this tutorial will go through the layout of a nmos transistor.
To begin the layout of a nmos transistor, first select the nactive layer in the LSW. Type 'r' to draw a rectangle, first selecting the start point, and then the end point. We want the dimension of this layer to be similiar to the nmos that was used in the previous inverter. Therefore, the length should be 3um and the width should be about 3.6 um (it is a general rule of thumb to make the width 3um + gate length, which equals 3.6 um).
To make sure that the dimensions of the layer are accurate, use the ruler function or type 'k'. Place the starting and stopping points of the ruler. You can make as many rulers as desired. If you want to remove the rulers, type 'K'.
Next, select the cc layer in LSW. 4 contacts need to be placed that have the size 0.6um by 0.6um. Using the rectangle function, place the first one in the upper right corner of the nactive layer, giving a 0.3um distance between the outer edges of the nactive layer. Place the next one directly below the first, with a 0.9um gap between the two. Place the third and fourth similiarly, but starting from the bottom left corner.
Next, surround the contacts created with the metal 1 layer (select metal1 in LSW) and make sure they overlap the contacts by 0.3um. It is easier to understand exactly how to design this by looking at the pictures provided.
These metal layers with their respective contacts are the drain and source of the transistor. To create the gate, we will select the poly layer from LSW. Create a skinny rectangle of the poly layer that goes straight through the middle of the nactive layer. Make sure that there is a 0.3um gap between the metal1 and poly layers and that the poly overhangs the nactive layer (on each end) by 0.6um.
Finally, for the nmos, select the nselect layer from the LSW and place it around the outside of the nactive layer so that there is 0.6um between the two layers (the upper and lower edges of the nselect layer will touch the poly layer).
When drawing the pmos, follow a similar procedure as with the nmos, but with the pactive and pselect layers instead of the nactive and nselect layers, and make the dimensions 6.0um by 3.6um. Make 4 contacts on each side instead of 2. Zoom out from the nmos and draw the layout for the pmos somewhere nearby. Make the contacts and metal layers on the pmos opposite as they were on the nmos (metal layer touching upper left and bottom right corners).
Now, select the nwell layer from the LSW and outline pmos with a 2.1um gap between the nwell and pactive layers.
Now that the layout for the pmos and nmos transistors have been drawn up, let's connect them to make an inverter. First, zoom out and move the nmos and pmos together so that there is 1.2um between the nwell and nselect layers and so that the poly layers are lined up. The next step is to connect the gates of the transistors together (the poly layer) and create a contact connected to the gate, made out of the metal1, poly, and cc layers. The cc should be 0.6um by 0.6um in dimension and the metal1 and poly layers should overlap the cc layer by 0.3um on all edges.
Next, using the metal1 layer, draw the supply busses for VDD and VSS. Stretch the source of the pmos metal layer to the upper edge of the poly layer. Now, create a 7.2um by 2.4um metal1 box centered about the nwell layer and connected to the metal1 layer of the source. Similarly, follow the above procedure for the nmos.
Extend the nwell layer 0.3um above the metal1 layer of the pmos. Then, place a strip (6.0um by 1.2um) of the pactive layer on the nmos and the same sized strip of the nactive on the pmos, both centered in the metal1 areas that were just placed. Place the pselect layer on top of the metal1 box of the nmos and the nselect layer on top of the metal1 box of the pmos. Evenly space out three contacts (by having 0.3um from the edges and 1.8um between each contact) using the cc layer within each strip. Each contact should be 0.6um by 0.6um. What you have just created are the substrate contacts.
Connect the drains of the pmos and nmos (the metal layers on the right of each transistor) using the metal1 layer.
The next step is to create some pins. You will need to create 3 input pins (IN, vdd!, and gnd!) and one output pin (OUT). If you type 'Ctrl+p', the Create Symbolic Pin window will appear. After this window has appeared, select the metal1 layer in the LSW. Back in the Create Symbolic Pin window, enable "Display Pin Name" and choose input in the "I/O Type" section for inputs and output for outputs. For each pin, type in the name and in the Virtuoso Layout Editing window, select the starting and stopping points of the pin shape (1.2um by 1.2um). Place "IN" on the small poly box you placed before. Place "vdd!" and "gnd!" on the right contacts of the pmos and nmos sources, respectively. Place "OUT" somewhere on the common drain metal1 layer. Observe the picture below for a better idea of how this should look.
First, save your layout. Then, select Verify -> DRC...
Make sure that the "Rules File" field contains "divaDRC.rul". This is the file that contains all of the design rules that the layout must adhere to. You do not need to worry about changing any of the other options. Select OK. Then, check the CIW to make sure there were no errors. If there were any errors, the layer that the error is pertaining to will be highlighted in the Virtuoso Layout Editing window. Also, in the CIW, it will tell you the design rule that has been violated. To find out about the specifics of the rule your layout has violated, download the list of the design rules here. Once you have found and fixed any errors, you are now ready to extract the layout.
Leave all of the default settings and verify that the "Rules File" is "divaEXT.rul". Select OK. Verify that there are no errors in the CIW. A new "extracted" cell view has been created in your library. You can verify this by checking in the Library Manager Window.
To check that the layout and schematic are the same, select Run. If the LVS succeeded, you should get a message saying so.
This message does not necessarily mean that there weren't any errors though, so in the LVS window, select Output to display the results of the check. If there weren't any errors, the output report should read "The netlists match". If the netlists didn't match, it may be because you used different names in the schematic from the names you used in the layout. There are other examples of why they won't match, but if you have followed this tutorial and the previous one, you shouldn't have any problems.
Lastly, to perform a post-layout simulation, we need to extract the layout. By doing this, we can compare the functionality of the previously built inverter to see how closely they match. In the LVS window, select Build Analog. Select OK when the Build Analog Extracted View window appears.