Vbat mode is a hardware-based power mode that maintains critical operations when a power loss occurs on Vdd. To enable Vbat mode a back-up power source must be connected to the Vbat pin. In Vbat mode the RTCC can run when there is no power on Vdd.
Not all 16-bit MCUs and DSCs support Vbat. Please check the datasheet of the device you are planning to use.
Running with Vdd
When Vdd is present, an on-board switch directs the input voltage to the power regulator. The regulator supplies power to the entire MCU core and peripheral registers.
Loss of Vdd
Vbat mode is entered whenever power source is removed from Vdd. The on-chip power switch detects the power loss from the Vdd and connects the Vbat pin into a low voltage regulator. The low power regulator supplies power to the RTCC (if enabled) and both Deep Sleep Retention registers (DSGPR0 and DSGPR1).
No peripherals other than the RTCC receive power in V.bat mode.. The contents of memory locations and registers other than the Deep Sleep retention registers are not retained with Vbat mode.
When Vdd is restored
When Vdd is restored the device experiences a Power On Reset (POR):
- All registers, except DSGPR0 and DSGPR1, are return to their reset state.
- The system oscillator is initialized per the Configuration bits.
- The Program Counter is set to execute the instruction located at 0x000.
The contents of the DSGPR0 and DSGPR1 are retained through the POR. These registers can be read at any time by the software.
Context Saving before Vbat is Entered
The loss of Vdd is typically a spurious and unplanned event. Applications requiring data other than RTCC be retained during a power loss must pro-actively save the data. The data can be saved to off-chip non-volatile memory or to the Deep Sleep Registers.
Any data stored to the DSGPR registers must be written twice (the repeat sequence). While these write operations do not need to be sequential, back-to-back writes are the recommended programming practice.