As a greater number of processor cores is integrated onto a single die, the design space for interconnecting these cores becomes more fertile. One manner to interconnect those cores is simply to mimic multichip multiprocessor computers of the past. Following the past, simple bus-based shared memory multiprocessors can be integrated onto a single piece of silicon. But, by following the past, we do not take advantage of the unique opportunities afforded by single-chip integration. Specifically, buses require global broadcast and do not scale to more than about 8 or 16 cores. Some multicore processors have used one-dimensional rings, but rings do not scale either because their bisection bandwidth does not increase as more cores as added.
|Original language||English (US)|
|Title of host publication||Designing Network On-Chip Architectures in the Nanoscale Era|
|Number of pages||25|
|State||Published - Jan 1 2010|
All Science Journal Classification (ASJC) codes
- Computer Science(all)