damascene n - an integrated circuit process by which a metal conductor pattern is embedded in a dielectric film on the silicon substrate. The result is a planar interconnection layer. The creation of a damascene structure most often involves chemical mechanical polishing of a nonplanar surface resulting from multiple process steps. A damascene trench is a filled trench. [1994 National Technology Roadmap for Semiconductors]
damage n 1 - of a single-crystal silicon specimen, a defect of the crystal lattice in the form of irreversible deformation that results from mechanical surface treatments such as sawing, lapping, grinding, sandblasting, and shot peening at room temperature without subsequent heat treatments. [ASTM F1241] Also see crystal lattice. 2 - any yield or reliability detractors other than those related to design, process specification violations, or particles. [SEMATECH]
DC test - A sequence of direct current (DC) measurements performed on integrated circuit pads to determine probe contact, leakage currents, voltage levels on input and output, power supply currents, etc. [1994 National Technology Roadmap for Semiconductors]
deep level impurity n - a chemical element that, when introduced into a semiconductor, has an energy level (or levels) that lies on the midrange of the forbidden energy gap, between the energy levels of the dopant impurity species. [ASTM F1241]
defect n - for silicon crystals, a chemical or structural irregularity that degrades the ideal silicon crystal structure or the thin films built over the silicon wafer. 2 - a pit, tear, groove, inclusion, grain boundary, or other surface feature that is either characteristic of the material or a result of its processing and that is not a result of the sample preparation. [SEMATECH] Also called anomaly.
defect density n - the number of imperfections per unit area, where imperfections are specified by type and dimension. [ASTM F127-84] Also see defect.
defect level n - the number of die in parts-per-million that are shipped to customers and that are defective even though the test program declares them to be good. [1994 National Technology Roadmap for Semiconductors]
defect, photomask n - any flaw or imperfection in the opaque coating or functional pattern that will reproduce itself in a resist film to such a degree that it is pernicious to the proper functioning of the microelectronic device being fabricated. [SEMI P2-86]
delamination n - in a cofired ceramic package, chip carrier, dual inline, pin grid array, etc., the separation of one ceramic layer from another. [SEMI G61-94] Also see package.
delay fault n - a fault that has the effect of causing a signal to appear late in arriving at a destination. [1994 National Technology Roadmap for Semiconductors]
design for test (DFT) n - design of logic circuits to facilitate electrical testing. [SEMATECH]
destructive physical analysis n 1 - the examination and testing of components to ensure proper operation and behavior. [Sandia Labs]
device n - a specific kind of electronic component (such as an MOS transistor, resistor, diode, or capacitor) on a die. The diode and transistor are referred to as active devices; the capacitor and resistor, as passive devices. [SEMATECH]
dew point n - the temperature at which liquid first condenses when vapor is cooled. [SEMI C3-94]
DFT - see design for test
die n (sing or pl) - a small piece of silicon wafer, bounded by adjacent scribe lines in the horizontal and vertical directions, that contains the complete device being manufactured. [SEMATECH] Also called chip and microchip. Obsolete: bar, slice.
die attach area n - the nominal area designated for die attaching to the package or leadframe. [SEMI G22-86] Contrast effective die attach area and die attach pad.
die attach pad n - the nominal area designated for die attaching to the package or leadframe.. Die attach pad is usually applied to leadframes. The term die attach area is usually applied to ceramic packages. [SEMATECH] Also see package and die.
die attach surface n - in a ceramic semiconductor package, a dimensional outline designated for die attach. [SEMI G33-90] Also see package and die.
die bonding (D/B) - an assembly technique that bonds the back side of an integrated circuit die to a substrate, header, or leadframe. [SEMATECH]
dielectric n 1 - a nonconductive material; an insulator. Examples are silicon dioxide and silicon nitride. [SEMATECH] 2 - a material applied to the surface of a ceramic or preformed plastic package to provide functions such as electrical insulation, passivation of underlying metallization, and limitations to solder flow. [SEMI G33-90]
dielectric isolation (DI) n - a nonconductive barrier layer grown or deposited between two adjacent regions on a die to prevent electrical contact between the regions. [SEMATECH] Also see isolation.
diffusion n - a high-temperature process in which desired chemicals (dopants) on a wafer are redistributed within the silicon to form a device component. [SEMATECH]
dimple n - on a semiconductor wafer, a shallow depression in a wafer surface with a concave, spheroidal shape and gently sloping sides. NOTE—Dimples are macroscopic features that are visible to the unaided eye under proper lighting conditions. [ASTM F1241]
DIP - acronym for “dual-in-line package”.
dislocation n - a line imperfection in a crystal that either forms the boundary between slipped and nonslipped areas of a crystal or is characterized by a closure failure of the Burger’s circuit. [ASTM F1241] Also called line defect. Also see slip.
dopant n - in silicon technology, a chemical element incorporated in trace amounts in a semiconductor crystal or epitaxial layer to establish its conductivity type and resistivity. [Adapted from SEMI M9-90 and M8-84] Also see conductivity type, n-type, and p-type.
dopant density n - in an uncompensated extrinsic semiconductor, the number of dopant impurity atoms per unit volume, usually given in atoms/cm3 , although the SI unit is atoms/m3 . Symbols: ND for donor impurities and NA for acceptor impurities. [ASTM F1241]
doping n - the addition of impurities to a semiconductor to control the electrical resistivity. [SEMI M1-94 and ASTM F1241]
drain n - one of the three major parts of a complementary metal oxide semiconductor transistor. [SEMATECH]
drain region n - a collection region that acquires principal-current charge carriers from a channel, the current being due to a voltage applied to the drain [JESD77].
edge crown n - an increase of epitaxial layer thickness around the periphery of the wafer arising from differences in deposition rate. [SEMATECH]
electrostatic discharge (ESD) n 1 - a sudden electric current flow, such as between a human body and a metal oxide semiconductor semiconductor, with potential damage to the component. [SEMATECH] 2 - the transfer of electrostatic charge between bodies at different electrostatic potentials. [SEMI E33-94]
energy-dispersive X-ray spectrometer n - a detector used to determine which elements are present in a sample by analyzing X-ray fluorescence for energy levels that are characteristic of each element. [SEMATECH]
epitaxial layer n - in semiconductor technology, a layer of a single crystal semiconducting material grown on a host substrate which determines its orientation. [SEMI M2-94 and ASTM F1241]
epitaxy (epi) n - a silicon crystal layer grown on top of a silicon wafer that exhibits the same crystal structure orientation as the substrate wafer with a dissimilar doping type or concentration or both. Examples are p/p+, n/n+, n/p, and n/n. [SEMATECH] Also see epitaxial layer.
ESD - see electrostatic discharge.
etch 1 n - a category of lithographic processes that remove material from selected areas of a die. Examples are nitride etch and oxide etch. [SEMATECH] 2 - in the manufacture of silicon wafers, a solution, a mixture of solutions, or a mixture of gases that attacks the surfaces of a film or substrate, removing material either selectively or nonselectively. [SEMI M1-94 and ASTM F1241] Also see anisotropic etch, preferential etch, dry plasma etch, reactive ion etch, and wet chemical etch.
etchant n - an acid or base (in either liquid or gaseous state) used to remove unprotected areas of a wafer layer. Examples are potassium hydroxide, buffered oxide etch, and sulfur hexafluoride. [SEMATECH]
etch pit n - a pit, resulting from preferential etching, localized on the surface of a wafer at a crystal defect or stressed region. [ASTM F1241]
eutectic n - alloy or solution with components distributed in the proportions necessary to minimize the melting point. [SEMATECH]
excessive leakage n - in the testing of semiconductors, current that is above the specified limit for the particular test being conducted. [Sandia Labs]
failure 1 n - the loss of ability of a component to meet the electrical or physical performance specifications that (by design or testing) it was intended to meet [JESD29] 2 n - a component that has failed [JESD29].
failure mechanism n - in failure analysis, a fundamental process or defect responsible for a failure. [SEMATECH]
failure mode n - in failure analysis, the electrical symptoms by which a failure is observed to occur. Failure mode types include a catastrophic failure that is both sudden and complete and degraded failure that is gradual, partial, or both, as well as intermittent failures. [Sandia Labs]
failure mode and effects analysis (FMEA) n - an analytically derived identification of the conceivable semiconductor failure modes and the potential adverse effects of those modes on the system and mission. [SEMATECH]
fault n 1 - an accidental condition that causes a functional unit to fail to perform its required function. [SEMATECH] 2 - a defect- causing out-of-spec operation of an integrated circuit. [SEMATECH] Also see exception condition and defect.
fault coverage n - the percentage of a particular fault type that a test vector set will detect when applied to a chip. [1994 National Technology Roadmap for Semiconductors]
fault dictionary n - a list of faults that a test vector will detect in a failing circuit, or a list of all such faults for each vector in a vector set. [1994 National Technology Roadmap for Semiconductors]
fault model n - a model of the behavior of defective circuitry in an integrated circuit. Physical defects result in improper behavior in a circuit that must be modeled in order for test patterns to be designed to properly detect them. Examples include stuck-at model, timing model, and bridging model. [1994 National Technology Roadmap for Semiconductors]
FET - see field-effect transistor.
FIB - see focused ion beam
field-effect transistor (FET) 1 n - a transistor consisting of a source, gate, and drain, the action of which depends on the flow of majority carriers past the gate from the source to the drain. The flow is controlled by the transverse electric field under the gate. [SEMATECH] 2 n - a transistor in which the condition is due entirely to the flow of majority carriers through a conduction channel controlled by an electric field arising from a voltage applied between the gate and the source [JESD77].
fishtails n - structures, attributed to substrate defects, either above or below the surface plane after epitaxial deposition; the “tails” are aligned in a particular crystallographic direction. [ASTM F1241] Also see crescents.
fissure - see crack.
flake n - material missing from one but not the other side of a semiconductor wafer. [SEMI M10-89]
flake chip - see chip and peripheral chip.
flaking - see peeling.
flip-chip n - a leadless, monolithic structure that contains an integrated circuit designed to electrically and mechanically interconnect to a hybrid circuit. Connection is made to bump contacts covered with a conductive bonding agent on the face of the hybrid. [SEMATECH] Also called controlled collapse chip connect or C4
fluorescence n - the emission of light as the result of, and only during, the absorption of radiation of shorter wavelengths. [IEEE]
Fluorescent Microthermographic Imaging n - a failure analysis technique that uses a temperature dependent fluorescent compound and an optical pumpiing source to image temperature changes on a semiconductor device with near optical spatial resolution. [Sandia Labs]
FMEA - see failure mode and effects analysis.
FMI - see Fluorescent Microthermographic Imaging.
Fourier Transform Infrared Spectroscopy n - an analytical tool to determine the composition of a material using an infrared laser.
Focused ion beam (FIB) n - an imaging tool that can be used to deposit or etch materials on wafers. A focused ion beam is often used in the etch mode to selectively cleave structures for failure analysis. It is also used in photomask repair for removing or adding material, as necessary, to make the photomask defect free. [SEMATECH]
Front end of line (FEOL) n 1 - in semiconductor processing technology, all processes from wafer start through final contact window processing [SEMATECH].
FTIR - see Fourier transform infrared spectroscopy.
functional pattern - see pattern, functional.
functional probe n - the electronic testing of die on a wafer to determine conformance to specifications. [SEMATECH]
functional test n - one or more tests to determine whether a circuit’s logic behavior is correct. [1994 National Technology Roadmap for Semiconductors]