Interfacing to the Core
The Memory Controller Block (MCB) provides a simple, reliable means of interfacing to a single component memory device. The MCB User Interface removes the complexities of DDR memory interfacing so that more engineering resources can be directed to the unique aspects of the FPGA design.
User (Fabric Side) Interface
The User Interface contains all the necessary signals for the user logic in the FPGA logic to interact with the command path and datapath of the MCB ports. It also includes the general clock and reset signals for the MCB as well as signals related to calibration, debug, and self-refresh operation. The User Interface can be configured to have anywhere from one to six ports.
From the User Interface perspective, the MCB provides a simple and sequential byte addressing scheme into the physical DRAM. The fact that DRAMs store data in fixed segments is abstracted by this scheme, allowing for a simple SRAM-like address interface.
The command path of the User Interface uses a simple 4-deep FIFO structure to hold pending commands. The instruction type, address, and burst length for the requested transaction are all loaded into this Command FIFO. The full flag signal from the command FIFO must be low for a new command to be accepted ino the FIFO when pX_cmd_en is asserted during the rising edge of pX_cmd_clk. Otherwise, the command is ignored.
(Xilinx Answer 43355) - Performing Writes
(Xilinx Answer 43356) - Performing Reads
(Xilinx Answer 43357) - Available DDR Commands
(Xilinx Answer 43358) - Masking Data
(Xilinx Answer 43359) - How many commands & data can be stored?
(Xilinx Answer 43360) - Addressing
(Xilinx Answer 35410) - How many commands can the design store?