The Internet of Things has become a ubiquitous term, to refer to a broad (and somewhat ill-defined) set of electronic products and potential applications – e.g., wearables, household appliances and controllers, medical applications, retail applications (signage, RFID), industrial automation, machine-to-machine communication, automotive control and communication, agricultural monitoring, etc.
Additionally, many references to the IoT include services associated with “the cloud”, as the repository for the data generated by connected devices. Regardless of your definition of the IoT, there are some unique characteristics of the SoC’s designed for these applications.
At the recent Linley Group Processor Conference, Frankwell Lin, President of Andes Technology, gave an insightful presentation on processor design considerations for IoT applications, and how Andes has recently enhanced their (soft IP) embedded core offering. A key takeaway was that IoT designs will need to leverage the power/performance benefits enabled by an extensible processor instruction set architecture for embedded cores.
There are some common characteristics of the IoT that are common across all interpretations:
- typically include sensors, actuators, cameras
- may require a digital signal co-processor, with a rich DSP instruction set)
- minimal (secure) software boot kernel
- low-bandwidth (secure) communication with the gateway, using protocols such as RFID, Bluetooth Smart, Zigbee, WiFi802.11ah, LTE Cat-0
- power management features for low power dissipation
(Frankwell reminded the audience that the design optimization constraint is actually not low power, but rather total energy consumption.)
- responsible for data collection, security of data transmission/storage, (perhaps some) client services
services:including remote services in the cloud
The client devices for IoT applications have an extremely diverse set of usage models. The design of an embedded processor core’s ISA for the general IoT workload involves a complex set of tradeoffs – too rich a set of core instructions and area/power will be wasted; too few, and performance will be compromised.
Another factor in selecting the optimum ISA is the resulting code size (and locality of instructions) for the application – the cost/area/power for code memory and instruction cache is another key consideration.
And, perhaps most significantly, there may be data processing algorithms that demand a unique approach – either hard-wired bypass logic, or more typically, additional programmable instruction(s) that augment the ISA of the general purpose core. A proprietary instruction may offer major performance and/or energy consumption improvements.
Andes Technology extensible ISA embedded core
Andes has implemented the Andes Custom Extension (ACE) interface to their E801-S embedded core. Their “COPILOT” development tool allows users to incorporate custom instructions.
The figure illustrates the general ACE architecture, highlighting the IP blocks that are generated by Andes with the customer-designed functionality.
The logic definition for this interface supports:
- single- or multi-cycle custom instruction latency
- sharing of logic among multiple custom instructions
- user-defined error status
- custom instruction interrupts
- memory accesses (through the baseline E801 core)
To illustrate the impact of adding a custom instruction, Frankwell used the example of a custom CRC-32 generation instruction:
Comparisons are provided between the ACE instruction logic with C-language compiled algorithms executing on the baseline embedded core – note the tremendous improvement in performance and energy consumption, with a very small number of additional logic gates required.
And, to complement the ACE RTL generation features, Andes provides the requisite instruction set simulator and software compiler support, performance profiling tools, and RTL verification environment infrastructure for the customer-defined instructions.
One final point that Franklin made during the subsequent Q&A after his presentation is definitely worth highlighting. For IoT client devices to be optimized, the “cost of entry” must be minimized. (“Kickstarter” and “Shark Tank” funding sources were mentioned by the audience, only half-jokingly.)
The comprehensive IP provided by Andes Technology – e.g., general purpose embedded cores, extensible ISA support, compiler and performance profiling tools – will provide a cost-effective solution to enable IoT market growth to accelerate.
Video of the presentation:Share this post via: