In previous papers Professor Chen's team has reported on a device that showed uniform bipolar resistance switching behavior with an operation below 100 nanoseconds and a resistance on/off ratio of more than 100 and greater than 10 years retention time.
In terms of cycling endurance the team has not yet done strict testing although they have put devices through thousands of programming and erase cycles, Professor Chen said. He added that achieving the cycling endurance of nanometric NAND flash memory at 10^4 or 10^5 cycles represented a relatively easy goal. "I don't see a problem exceeding flash memory. Whether it could be used as a DRAM at 10^10 or 10^11 cycles I don't know."
The use of different electrodes is significant as there is a work function dependency in the switching. However, the use of molybdenum and platinum in particular is not required, said Professor Chen. "We chose platinum as the top electrode because it is very durable; useful for test devices."
In the present arrangement the change from high resistance state (HRS) to low resistance state (LRS), which Professor Chen calls onswitching, occurs at about -1V while the switching from LRS to HRS can be tuned to take place at voltages down to 1 volt but in the range 1-V to 10-V. Reading the state of the memory requires a lower voltage of about 0.5-V but could be taken down to 0.2-V, Professor Chen said.
These memories are not thought to be filamentary and unlike other ReRAMs, the insulator-metal transition in nanometal ReRAMs can be triggered by UV irradiation without an electric field.
Professor Chen's group has not yet made any devices with nanometer-scale lateral minimum geometries and nor has it produced any arrays of the memory devices. One of the reasons for this is that as the memory device is bipolar it will require a circuit isolation device to prevent cross-talk in an array.
The development of smaller geometry devices and arrays represents an obvious next step for the research. "We would like some companies to get interested and see if it can be done in a wafer fab setting," Professor Chen said.
Some more details from this group are at Adv. Mat. 23, 3847-3852 (2011). It largely reflects what has been reported here. However, capacitance measurements are missing which should be normally used to evaluate the charge trapping.
I see the distinction you are going after, a distributed vs. more focused filament path. But the way to show this is to compare R vs. size. If R is weakly dependent on size, as was shown in the thesis, it is more likely to be at least not so evenly distributed as would be imagined. I'll check this against the foils from the event, if they are available soon.
This paper and 11 other exciting talks are scheduled for the IEEE San Francisco Bay Area Nanotechnology Council's 8th Annual Full Day Symposium -"Emerging Non-volatile Memory Technology" on April 6th. Register at www.ieee.org/nano where you can find the abstracts for the other papers
Resistron-If you fabricate a device with a volume fraction of Pt in the range 30% close to the value of the percolation limit, (i.e 33%), where the probability of a continuous path becomes 1, then there will be in 3D many possible similar discontinuous shorter paths. I think it is wrong to describe this as a standard filamentary RRAM, whatever that is. Sure you could lump these under your definition of "predefined filaments". The results in work already published suggest a good correlation of resistance with area, suggesting the insulating state is NOT single filament like many of the reported RRAM and ReRAMs. I think you need to understand the role of the spreading resistance in the values reported by Prof Wei and colleagues for the conducting state, without that you might conclude the results for the conducting state are substantially independent of area and are therefore for a single conducting filament.
When operating near the 33% volume fraction limit there is also a probability of many paths where there are short continuous chains of Pt atoms that do not reach the distance between the electrodes, so they might be considered as nano metallic strands, there can still be traps between those chains that allow the device to work as reported, even if the strands become negatively charged the will offer some form of Coulombic repulsion.
I would suggest if you have the opportunity you follow Peter Clarke's advice here above and attend Prof Wei's presentation. Also read the report of the work from on Rice NV RAM, reported in EETimes today-that is clearly a single filament device. Your standard filamentary RRAM if you like.
I understand that there are characteristics of resistance switching behavior and V-I-R curves that can be used to distinguish between filamentary and non-filamentary behavior. These are things which I did not go into here.
I suggest that those who are interested in more detail get along to the TI Conference Center at
2900 Semiconductor Drive, Santa Clara, California on Friday, April 6. OR try and get hold of Professor Chen's slide set from the event, perhaps from the IEEE.
Having read his student's thesis, I think what they got is a standard filamentary RRAM, with pre-defined filaments, marked by Pt and pores characteristic of co-sputtered films. Filaments can consist of charge-trapping defects of course. But the defects they show are nm-scale rather than atomic.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.