The P6 microarchitecture
is the sixth generation Intel x86 microprocessor
architecture, released in 1995
. It was succeeded by the NetBurst
microarchitecture in 2000
, but eventually revived in the Pentium M
line of microprocessors. The successor to the Pentium M variant of the P6 microarchitecture is the Intel Core microarchitecture
From Pentium Pro to Pentium III
The P6 core was the sixth generation Intel microprocessor in the x86 space. The first implementation of the P6 core was the Pentium Pro
CPU in 1995, the immediate successor to the original Pentium design (P5).
Some techniques first used in the x86 space in the P6 core include:
- Speculative execution and out-of-order completion (called "dynamic execution" by Intel), which required new retire units in the execution core. This lessened pipeline stalls, and in part enabled greater speed-scaling of the Pentium Pro and successive generations of CPUs.
- Superpipelining, which increased from Pentium's 5-stage pipeline to 14 of the Pentium Pro, and eventually morphed into the 10-stage pipeline of the Pentium III, and the 12- to 14-stage pipeline of the Pentium M.
- Integrated L2 cache that runs at the full speed of the processing core, instead of the earlier designs of off-die (on motherboard) cache, which runs at a fraction of the CPU frequency.
- Wider 36-bit physical address bus to support more than 4 GiB of physical memory (the linear address space of a process was still limited to 4 GiB).
- Register renaming, which enabled more efficient execution of multiple instructions in the pipeline.
The P6 architecture lasted three generations from the Pentium Pro to Pentium III, and was widely known for low power consumption, excellent integer performance, and relatively high instructions per cycle (IPC). When the new NetBurst (P68) architecture was conceived, initially in the Willamette core, which had relatively low IPC and less efficient overall design both in terms of power consumption and throughput efficiency, the P6 line of processing cores were largely thought to be abandoned.
Revived architecture in Pentium M (Banias and Dothan)
Upon release of the Pentium 4's mobile variant, it was quickly realized that the new NetBurst core was not ideal for mobile computing. The Netburst-based processors were simply not as efficient per clock or per watt compared to their P6 predecessors. Pentium 4-Mobile ran much hotter than the Pentium III-M and didn't offer significant performance advantages. Its inefficiency affected not only the cooling system complexity, but also the all-important battery life.
Intel, realizing that their new architecture wasn't the best choice for the mobile space, went back to the drawing boards for a design that would be optimally suited for this market segment. The result was a hybrid, modernized P6 design called the Pentium M:
- Socket 479. Electrically similar to Socket 478, but not compatible.
- Faster front side bus. With the initial Banias core, Intel adopted the 400 MT/s Netburst bus. The Dothan core moved to the 533 MT/s bus, following Pentium 4's evolution.
- Larger L2 cache. Initially 1 MiB, then 2 MiB in Dothan. Dynamic cache activation by quadrant selector from sleep states.
- SSE2 support.
- Pipelining lengthening by 3-4 stages for improved clock scaling.
- Dedicated register stack management.
- Addition of global history to branch prediction table.
- Micro-ops Fusion of certain sub-instructions mediated by decoding units. x86 commands can be combined into fewer RISC micro operations.
- Enhanced SpeedStep III (EIST). The processor can clock down to a fraction of its maximum speed and voltage when idle, bringing power usage down to only a few Watts.
The Pentium M was the most power efficient processor for notebooks for several years, consuming under 30 Watts at maximum load and a mere 4-5 Watts while idle. The processing efficiency gains brought about by its modernization allowed it to rival the Netburst processors clocked nearly one gigahertz higher and equipped with much more memory and bus bandwidth.
Pentium M's primary shortcoming was in the floating point realm. The P6 core had reasonable floating point performance throughout much of its lifetime, but the newer AMD Athlon and Athlon 64 cores, along with the powerful floating point SIMD capabilities of NetBurst processors, outclassed it. Although Intel implemented SSE2 in Pentium M, the implementation was not equal to that within the Athlon 64 or Pentium 4. So, on tasks where Pentium M was relying heavily on its floating point unit instead of its cache and integer performance, it would present disappointing performance.
Intel Core (Yonah)
The Yonah CPU
was launched in January 2006
under the Core
brand. Single and dual-core versions were sold under the Core Solo and Core Duo brands respectively (the Solo processor being a Duo, but with one disabled core). These processors provided partial solutions to some of the foregoing Pentium M
's shortcomings, by adding to its P6 microarchitecture
- SSE3 Support
- Dual-core technology with shared L2 cache (restructuring processor organization)
This resulted in the interim microarchitecture for mobile only CPUs, part way between P6 and the next all processor Core microarchitecture introduced with the CPUs branded Core 2, Pentium Dual-Core, Celeron, and Xeon.
It is important to note, that some Pentium Dual-Core branded CPUs (T2060, T2080 and T2130) are Yonah-based.
P6 based chips
Whilst all these chips are technically derivatives of the Pentium Pro the architecture has gone through several radical changes since it's inception.