While continuously improving IC and SOC technologies, higher clock rates, and more powerful processors are music to the design engineersí ears, the headaches of test engineers are getting worse and worse.
The ever decreasing test access was the worrying factor in the past, but a new problem arose in recent years with the dramatically increasing speed of the signal transmission.
The resulting failure phenomena and test access limitations have an inevitable impact on the efficiency and practicality of test strategies.
It is apparent that structural tests for detecting connectivity faults (opens and shorts) have huge advantages regarding test automation, diagnosis, and deterministic fault coverage. However, test coverage for dynamic failure phenomena demands higher test speed in order to carry out at-speed tests.
For this, functional tests are more suitable, although test development effort is enormous and failure diagnosis is rather limited. A single test technique that meets all requirements is neither existent nor on the horizon. Instead a suitable mix of techniques is the way to go. The combination of boundary scan and emulation test can be considered as a particularly interesting approach.
The basic idea of emulation tests is not new; in fact, it was successfully used and supported with device-specific tools since the early 1980s. Processor specific Pods, inserted into the device under testís (DUT) socket instead of the actual device (e.g. a MPU) or for software verification in-circuit-emulators (ICE) were used.
Today, device emulation is done with on-chip emulation (OCE) circuitry. The JTAG Test Access Port (TAP) defined in IEEE Std. 1149.1 is often applied as a communication port in various implementations and deviations. The important aspect is that the DUT core can be controlled with normally just 5 wires and without loss of performance. This benefit can be exploited in JTAG TAP controlled emulation tests. Figure 1 shows the complementary character of both techniques. Emulation tests can be considered as classic functional tests with associated advantages and disadvantages.
Fig 1: The pros and cons of boundary scan and traditional JTAG emulation test.
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A combination of both techniques, boundary scan and emulation test, seems absolutely reasonable, however respective system solutions must exploit the synergy between both methods.