Nicole Chubb and Jenny Mankin
In a typical NAND gate, when one input switches from 0 to 1 while the other stays at 1, the falling edge of the output waveform is mismatched against the falling edge of the output waveform when a 0 to 1 transition occurs on the other input because of the body effect in the nMOS . To alleviate this problem, a modified NAND is used. With the addition of two more nMOS transistors and cross-coupling oft the gates, both the pull-down and pull-up paths of the output are matched with respect to the two inputs to ensure good symmetry of the output waveform. [pp. 1224-1225]
(Old word count: 104 words. New word count: 103 words)
Circuit A Circuit B
The original passage indicates that the second NAND gate has better waveform matching because of the body effect. In Circuit A, after the inputs switch from anything to both high, both NMOS transistors are on. Figure 1 below shows the circuit with both inputs at logic high:
Figure 1: Circuit A, with both inputs at logic high.
Notice that the body of the upper NMOS transistor is at ground, while the source of that transistor is at some voltage larger than zero, thus producing a body effect. The outcome of the body effect is to raise the turn-on voltage for that transistor, specifically by the formula
VT = VTO + g(√( 2 |fF|+ VSB ) - √( |fF| ) ).
Therefore, it will take that NMOS slightly longer to turn on, leaving no path to conduction. With no path to ground (but also, since the PMOSs are off), Vo is left hanging, and will discharge very slowly until that NMOS transistor turns off and there is a direct path to ground. This problem only occurs when that NMOS transistor was undergoing a transition from the (0,1) or (0,0) inputs to the (1,1) inputs. If the input to the upper NMOS was already high, and input to the lower NMOS was previously low, then the upper NMOS is already turned on, and the lower NMOS (which is turning on) has its source and body at the same potential so there is no body effect.
This theory can be checked with a PSPICE simulation to show the body effect does play a role in the output of the circuit, but it is very small. Figure 2 below shows this effect; it contains overlaid output waveforms, with one waveform showing the (0,1) to (1,1) transition of the upper NMOS (which should show body effect) and the other showing the output of a (1,0) to (1,1) transition (which should show no body effect).
Observe that the waveform indicating the low-to-high transition is always a fraction of a nano-second behind the waveform indicating no transition. This is because the body effect delays the output voltage discharge to ground.
Figure 2: a) PSPICE output showing discharge after high-to-low upper input transition (purple) and no transition (green) and b) enlargement of a portion of the output to show contrast.
Circuit B is designed differently. The figure below shows Circuit B, but with Figure 3a with one input high and one input low, and Figure 3b with both inputs high.
Figure 3: Circuit B, with a) 0V on the input to the upper NMOS and b) VDD on the upper NMOS. In both cases the input to the lower NMOS is VDD.
As soon as the transition is made from the (0,1) to (1,1) input voltages, N2 turns on. Because its source is tied to the same potential as its body, it has no body effect. However, transistor N1 will have a body effect, because its body is not tied to the same potential as its source, so it will take slightly longer to turn on. However, in this circuit, the output voltage is tied to both transistors, so the N1 branch will quickly discharge the output to ground, regardless of how long it takes N1 to turn on. By comparison, this same transition produced a body effect in Circuit A. With Circuit B, the same thing happens with a (1,0) to (1,1) transition as did with the (0,1) to (1,1) transition: no body effect. Likewise Circuit A had no body effect for this transition. This explains the symmetry described in the passage: Circuit B has better symmetry because the output waveform is the same regardless of which type of transition is occurring. Observe the PSPICE output below in Figure 4, with the (0,1) and (1,0) to (1,1) transition output waveforms overlaid.
Figure 4: a) PSPICE output showing discharge from (0,1) to (1,1) transition (purple) and (1,0) to (1,1) (green) and b) enlargement of a portion of the output to show contrast. The purple waveform does not appear because it is the perfect match of the green waveform.
This time there is no difference between the waveforms, even blown up to a large scale. This indicates almost perfect symmetry, as stated by the authors of the passage.
In addition to improving the symmetry of the NAND gate, Circuit B also improves upon the fall time and propagation delay. For both circuits, when both inputs are high, the output voltage discharges from high to low. Consider the output waveforms, Figure 5 below:
Figure 5: Output waveform for Circuit A (green line) and Circuit B (pink line). The region of interested is highlighted in red.
The red box indicates the region of interest: namely, where both inputs are high. The top (green) waveform shows the output of Circuit A, and the bottom (pink) output shows the output of Circuit B. Notice that it takes Circuit A longer to discharge completely: approximately 4ns longer. Additionally, the propagation delay is nearly twice as long for Circuit A.
One reason for the improvement in fall time is due simply to the addition of two more NMOS gates. Observe two circuits below: Circuit A with inputs both high (Figure 6a) and Circuit B with both inputs high (Figure 6b).
Figure 6: Circuit A (a) and Circuit B (b), with both inputs equal to VDD. All PMOS transistors are off and all NMOS transistors are on.
In both cases, the PMOS pullup transistors turn off, and the NMOS pulldown transistors stay on. However, in Circuit A, there is only one conducting path to ground, and in Circuit B there are two conducting paths to ground. Thus, the voltage can discharge more quickly.
With the use of only two NMOS transistors, VA controls the PMOS and NMOS junction. When VA is high, current flows through the bottom half of the circuit; otherwise, the PMOS circuits have no connection to the lower half of the gate. When VA is low, there is a voltage drop across that node, so that when VB is pulled low, the capacitor does not need to take time to charge, and it begins to discharge 20ps faster than when VA is pulled from low to high.
Figure 7: Output of V3 and voltage at node 4 with respect to VINA and VINB.
With the addition of two more NMOS transistors, the NAND gate becomes more symmetrical, and both inputs have equal control over the NMOS section of the gate. The capacitor is also charged when either input is high. Also, the start time of the capacitor discharge does not depend on which input goes from low to high, so the capacitor discharges at the same rate for any combination of input toggling.
Figure 8: Output of V30 and voltages at nodes 40 and 50 with respect to VINA and VINB.
With the use of only two NMOS transistors, the capacitor also takes longer to discharge than the NAND with four NMOS transistors since it is driving less current. This accounts for an increase in the propagation delay. With only two NMOS transistors, the propagation delay for tPHL is 1.98ns. With four NMOS transistors, the propagation delay is tPHL = 1.08ns. With the output voltage discharging across two pairs of NMOS transistors in parallel, the output is pulled to VOL faster.
Figure 9: Transfer curve annotated with propagation delay for V3
Figure 10: Transfer curve annotated with propagation delay for V30
PSPICE Deck Used:
The following PSPICE code came from Dr. Brauns EE307 Website. The only change made was nominal: Transistors
MNA2 and MNB2 were named differently in the given figure than in the PSPICE deck. The nodes were unchanged.
* EE 307 CMOS NAND Gates for F04 MoHAT Project
Vdd 1 0 2.5
VinA 2A 0 PULSE(0 2.5 10ns 0.25ns 0.25ns 29.5ns 40ns)
VinB 2B 0 PULSE(0 2.5 0ns 0.25ns 0.25ns 19.5ns 30ns)
R2 2A 20A 1n
R3 2B 20B 1n
* Standard NAND
MPA 3 2A 1 1 PMOD1
MPB 3 2B 1 1 PMOD1
MNA 3 2A 4 0 NMOD1
MNB 4 2B 0 0 NMOD1
CL1 3 0 10p
* Symmetrical NAND
MPA2 30 20A 1 1 PMOD1
MPB2 30 20B 1 1 PMOD1
MNA1 30 20A 40 0 NMOD1
MNB1 40 20B 0 0 NMOD1
MNA2 30 20B 50 0 NMOD1
MNB2 50 20A 0 0 NMOD1
CL2 30 0 10p
.MODEL NMOD1 NMOS (L=1U W=50U KP=200U GAMMA=0.9 phi=0.6 lambda=0.02 VTO=0.7)
.MODEL PMOD1 PMOS (L=1U W=50U KP=100U GAMMA=0.9 phi=0.6 lambda=0.02 VTO=-0.7)
.TRAN 0.0 200ns 0ns 20ps
.PRINT TRAN V(1) V(2A) V(2B) V(20A) V(20B) V(3) V(4) V(30) V(40) V(50)
*The Location statements are particularly optional:
*LocationOf MPA X: 120 Y: 110 R: [4, 8, 1, 2]
*LocationOf MPB X: 180 Y: 110 R: [4, 8, 1, 2]
*LocationOf MNA X: 180 Y: 160 R: [1, 8, 4, 2]
*LocationOf MNB X: 180 Y: 240 R: [1, 8, 4, 2]
*LocationOf MPA2 X: 450 Y: 110 R: [4, 8, 1, 2]
*LocationOf MPB2 X: 540 Y: 100 R: [4, 8, 1, 2]
*LocationOf MNA1 X: 450 Y: 170 R: [1, 8, 4, 2]
*LocationOf MNB1 X: 450 Y: 300 R: [1, 8, 4, 2]
*LocationOf MNB2 X: 540 Y: 190 R: [1, 8, 4, 2]
*LocationOf MNA2 X: 540 Y: 270 R: [1, 8, 4, 2]
*LocationOf Vdd X: 40 Y: 180 R: [1, -1, 2, -1]
*LocationOf VinA X: 90 Y: 180 R: [1, -1, 2, -1]
*LocationOf VinB X: 110 Y: 260 R: [1, -1, 2, -1]
*LocationOf R2 X: 350 Y: 140 R: [-1, 2, -1, 1]
*LocationOf R3 X: 290 Y: 300 R: [-1, 2, -1, 1]
*LocationOf CL1 X: 250 Y: 170 R: [1, -1, 2, -1]
*LocationOf CL2 X: 620 Y: 180 R: [1, -1, 2, -1]
*LocationOf V(1) X: 210 Y: 40 R: 0
*LocationOf V(0) X: 200 Y: 340 R: 0
*LocationOf V(2A) X: 100 Y: 140 R: 0
*LocationOf V(2B) X: 110 Y: 200 R: 0
*LocationOf V(20A) X: 380 Y: 140 R: 0
*LocationOf V(20B) X: 320 Y: 300 R: 0
*LocationOf V(3) X: 230 Y: 130 R: 0
*LocationOf V(4) X: 180 Y: 180 R: 0
*LocationOf V(30) X: 590 Y: 130 R: 0
*LocationOf V(40) X: 450 Y: 230 R: 0
*LocationOf V(50) X: 540 Y: 240 R: 0