Editor’s note: I am pleased to present a nice article regarding IEEE 1588 and other communication network accurate transfer of data and time of day. We welcome Silicon Labs guest blogger, Kimberly Tuck, a Senior Systems Engineer at Silicon Labs.
Communication networks have relied on a robust synchronization distribution scheme for many years and it’s becoming even more important in today’s evolving networks. Synchronization is needed between communication networks to efficiently transfer data. Mobile networks rely on both frequency and phase synchronization to support high-speed data transmission and manage call hand-off as subscribers move from one cell area to another. Data centers need synchronization to maintain accurate time of day for distributed computing and high frequency trading. It’s important that these systems are designed with redundant synchronization architectures to prevent single points of failure.
A widely used synchronization distribution architecture uses two centralized timing cards with multiple line cards that communicate over a common backplane. This architecture provides a redundant master/slave timing system where timing cards are used to deliver the system clock to the line cards. The two timing cards provide redundancy, ensuring uninterrupted synchronization and system robustness. The slave acts as the backup to the master in case of a failure. In this type of architecture one timing card is designated as the master and the other the slave. The master will select the input reference clock. The slave, which is the backup timing card, will closely track the master system clock and provide redundant system clocks that are aligned by both frequency and phase to the master. In case of a failure on the master timing card, the slave quickly becomes the master without interruption to the line cards.
Silicon Labs offers products such as the Si5348 network synchronizer clock generator for these timing card applications. This Stratum 3/3E-compliant device can be used in Synchronous Ethernet/IEEE 1588 packet-based applications. For line card applications, Silicon Labs offers products such as the Si5345 clock to provide synchronization, jitter cleaning, clock multiplication and high-speed SerDes clocking.
Let’s take a closer look at the process and behavior by which a timing card master and slave perform this type of master/slave switch during a failure or a routine maintenance event in networking equipment. The events and settings for both the timing and line card clocks are described in detail.
Master – Slave Timing Card Redundancy System Block Diagram
Figure 1 provides an example of a master/save timing topology. Each of the line cards has access to the clocks generated by both timing cards.
The master locks to external synchronization sources and provides reference clocks to the line cards and to the slave. A crossover link between the master and slave allows the slave to lock to the master. This technique minimizes the phase difference of the clocks that are received at the line cards.
The master is in control of the timing in a system, providing precise and accurate timing to the line cards. The master selects a reliable reference as its source of synchronization. The loop bandwidth of the master is selected to meet wander filtering requirements. For a system meeting SONET Stratum-3/3E requirements, a loop bandwidth of 0.1Hz is selected.
The function of the slave is to track the master’s output clock and to provide a redundant clocks to the line cards. If a failure occurs at the master, the slave must be ready to take over mastership. To support this capability, the slave and master must be wired symmetrically to each other in a redundant fashion so that they can switch roles in an instant. Figure 1 illustrates this symmetry. The output from each timing card is wired to one of the inputs of the other timing card. Both master and slave have access to a reliable external references. The line cards can switch between the two timing card inputs during the switchover process to ensure they always follow the timing card determined to have the highest reliability.
Sequencing Details of a Master to Slave Switch Process
At system power up, one of the timing cards is configured as the master (shown in red in Figure 1) and the other as the slave (shown in grey). For this application, the master network synchronizer has a PLL bandwidth of 0.1 Hz while the slave has a PLL bandwidth of 100 Hz. The slave bandwidth is set much wider than that of the master to allow quick response time for the slave to track the movements of the master.
The master is configured with a specific external input priority with hitless switching enabled. The slave is connected to the same input clocks as the master, but in slave mode, the slave is configured to track the master. This is shown as IN1 on the slave timing card depicted in Figure 1. The other input connections are there for symmetry if the slave must switch over to master mode.
The line cards are configured to prioritize the input from the master (shown in IN0 on the line card in Figure 1). If a failure is detected on the master or a routine switch is initiated, the line cards automatically switch over to IN1. Hitless switching is enabled on the line cards, and their PLL bandwidths are set to 100 Hz.
A master-to-slave switch can be forced as a routine process, or it can be initiated due to a failure condition on the master.
Table 1 summarizes the sequence of events that occurs during a master/slave switch process.
Master/Slave Switch Sequence
In step 1 the master starts off locked to the external reference with a bandwidth set to 0.1 Hz while the slave is locked to the master with a bandwidth set to 100 Hz. The line card is locked to the master. In step 2, the host processor then forces the slave into holdover during a routine master-to-slave switch. If a failure occurs, the loss of signal (LOS) fault is detected on the slave, and the slave automatically enters the holdover state.
The line card then switches inputs from the master to slave in step 3, locking to the slave. Then the slave is immediately configured to the original master settings in step 4. The slave is forced to exit from holdover and is now considered the new master in step 5. The new master goes through a lock acquisition to the 0.1 Hz bandwidth settings, and the line card is then locked to the new master. The old master is reconfigured as the slave with a 100 Hz bandwidth and is locked to the new master.
Redundant network synchronizers are used in a master/slave configuration to provide system-level protection in the event of a failure condition. The switching process from the master timing card to the slave timing card can happen seamlessly with less than 1 ns of phase transient when high-performance network synchronizers and line card PLLs are used. Master/slave timing redundancy plays a critical function in edge/metro aggregation equipment to ensure highly reliable operation.