The divide instruction causes a 32-bit value to be divided by a 16-bit word from core storage. Result of the operation is placed in the accumulator; the remainder is placed in the accumulator extension.
Before the divide operation is started, the 32-bit value must be loaded into the accumulator and accumulator extension. (The units position is in bit 15 of the accumulator extension.) The divide instruction then addresses a 16-bit word (in core storage) that is used as the divisor. Examples of the arithmetic are:
The names of the values in the operation are:
The sign of the remainder is always the same as the sign of the original dividend. Before the operation, bit 0 of the accumulator specifies the sign of the dividend: bit 0 = 0 specifies a positive dividend; bit 0 = 1 specifies a negative dividend. Therefore, the value of bit 0 of the accumulator extension (after the operation when the extension contains the remainder) is the same as the original value of bit 0 of the accumulator (when it contained the original dividend).
The sign of the quotient is determined as follows:
If a 16-bit dividend (in the accumulator) is the result of some prior operation, it must be shifted to the right 16 places into the accumulator extension before the divide operation is performed. (A shift-right-accumulator-and-extension instruction can be used for this purpose.)
There are no addressing exceptions for the divide instruction; all forms of addressing that are described under "Effective-Address Generation" apply to the D instruction.
The largest dividend that can be correctly operated on is 230 + 215 - 1 (1,073,774,591 decimal) if divided by the largest negative divisor, -215 (-32,768 decimal).
Indicators: The carry indicator is not affected during a divide operation. The overflow indicator must be reset to 0 before the divide operation if it is to be used. When the overflow indicator is initially at a value of 0, it is set to 1 during a divide operation for either of two conditions:
|Assembler Language Coding||Hexadecimal Value||Description of Instruction|
|D||DISP||A8XX||Divide A and Q by contents of CSL at EA (I+DISP)|
|D||1||DISP||A9XX||Divide A and Q by contents of CSL at EA (XR1+DISP)|
|D||2||DISP||AAXX||Divide A and Q by contents of CSL at EA (XR2+DISP)|
|D||3||DISP||ABXX||Divide A and Q by contents of CSL at EA (XR3+DISP)|
|D||L||ADDR||AC00XXXX||Divide A and Q by contents of CSL at EA (Addr)|
|D||L||1||ADDR||AD00XXXX||Divide A and Q by contents of CSL at EA (Addr+XR1)|
|D||L||2||ADDR||AE00XXXX||Divide A and Q by contents of CSL at EA (Addr+XR2)|
|D||L||3||ADDR||AF00XXXX||Divide A and Q by contents of CSL at EA (Addr+XR3)|
|D||I||ADDR||AC80XXXX||Divide A and Q by contents of CSL at EA (V in CSL at Addr)|
|D||I||1||ADDR||AD80XXXX||Divide A and Q by contents of CSL at EA (V in CSL at "Addr+XR1")|
|D||I||2||ADDR||AE80XXXX||Divide A and Q by contents of CSL at EA (V in CSL at "Addr+XR2")|
|D||I||3||ADDR||AF80XXXX||Divide A and Q by contents of CSL at EA (V in CSL at "Addr+XR3")|
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